1. Field of the Invention
The present invention is related to a clock input control circuit, and particularly to a clock input control circuit which controls on/off of the inputting of a clock signal for synchronizing the operation in a device.
2. Description of the Related Art
Generally, in an LSI (Large Scale Integrated Circuit), there is provided an interface control circuit for use with the passing of external signals and data for internal circuits. Provided in this interface control circuit are circuit blocks such as shown in FIG. 6. That is, there are provided circuit blocks such as a parallel port 15 for internally receiving parallel data or outputting them to the outside, a serial port 16 for passing serial data, and an interruption control circuit 17 for accepting external interruptions. In addition, reference numeral 18 is a processor core, and 19 is an LSI chip. In the same figure, parallel data, serial data, and interruption data represent external data signals. These data are not synchronized with the internal clock signal. Such signals are called asynchronous signals. If such asynchronous signal is directly processed in the circuits within the LSI, a malfunction due to timing violation can be caused. Thus, the processing in the internal circuits requires synchronization with the internal clock. For this, usually the synchronization of an external asynchronous signal 118 with an internal clock 120 is performed using a synchronizing circuit as shown in FIG. 7.
That is, a flip-flop (FF) 20 having an asynchronous signal input to the input terminal 118 is used, and the internal clock of the device is applied to the clock input terminal 120 of the FF 20. By such synchronizing circuit, a synchronizing signal synchronized with the internal clock is obtained from the output terminal 119.
The above described circuit had a defect that it was difficult to make the power consumption low by clock gating, or the effect on it was low.
One of the conventional techniques for achieving a digital circuit of low power consumption is clock gating. The clock gating is a technique in which a gate circuit is interposed at some midpoint of a clock tree to stop the clock given to the blocks in a predetermined range, thereby for reducing the power consumption. If the clock gating is performed, the operation of a block for which the clock is stopped by the clock gating also stops. Accordingly, this technique can be used only if the time over which the particular block is not used is known.
However, for a circuit block to which an external asynchronous signal is input, the timing of change in the a synchronous signal is unknown to the internal circuit. Thus, the period of time during which the clock is stopped could not be set, so the power consumption reduction method by the clock gating technique could not be used.
An art for solving the above problem is described in Published Unexamined Patent Application No. 8-202654. In this publication, a technique is proposed in which the operation rate of the internal circuit is reduced by synchronizing the sampling cycle of a circuit for synchronizing an external asynchronous signal with the clock cycle of an external signal which generally has a longer cycle than the internal clock signal.
However, in this technique, since the operation is si performed in synchronism with the clock cycle of the external gnal even in the period over which the external asynchronous signal performs no operation, there is a defect that the effect of enabling low power consumption by the clock gating is limited.